As integrated circuit process technologies are pushed to produce parts having greater device densities, the dimensions of particular devices such as a field effect transistor (FET) are forced to shrink. As the channel lengths of the FETs are reduced to increase device density, consideration must also be given to the channel depth, that is, the depth of impurity doping in the channel region. If the channel is too deep with respect to the source/drain regions, problems will result with undesirable high capacitance to the source and drain. Other problems include the channel-p-n-junction depth in "buriedchannel" type devices which are widely used in CMOS technology. The deeper the channel-p-n-junction depth is, the more prone the device is to undesirable leakage currents. These problems are particularly acute for p-channel devices. As is well known in the art, impurities which are placed within the structure of an integrated circuit device under construction will be significantly redistributed by subsequent high temperature (greater than 900.degree. C.) thermal cycles. Thus, impurities located in a channel at one step in the process may be driven deeper during subsequent thermal cycles. When devices were larger, some redistribution could be tolerated and the devices would still perform properly. However, as wafer fabrication processes have become more complex and more thermal cycles have been added, with the advent of extremely small devices, it becomes more difficult to have the channel depth placed in its proper position at the end of the processing steps.
A similar problem occurs in the fabrication of capacitors. Pressures to shrink capacitor plates cause designers to increase capacitance by increasing the doping levels at the substrate surfaces. However, subsequent thermal cycles redistribute the impurities deeper and weaken the effects of the extra doping. In addition, as device structures become more exotic, more reliance is placed on exact positioning of the impurity regions. Thus, it would be advantageous if the number of thermal cycles could be reduced in the processing of an integrated circuit.
Another constant concern is the elimination of fabrication steps which may complicate the process and introduce errors. One known method of reducing the number of fabrication steps is to use in situ doped polycrystalline silicon or amorphous silicon, both of which are loosely termed "polysilicon", in contrast to doping the polysilicon after it is formed. Doping amorphous silicon in situ, as it is formed, only requires reaction temperatures on the order of about 575.degree. C. and polycrystalline silicon may be deposited at 625.degree. C., in contrast to the case where the polysilicon is first formed and then doped, where the impurity must be distributed throughout the polysilicon at a high temperature on the order of 900.degree. C. or more. While both of these temperatures may seem high, it is known that dopant positions are maintained for long periods at 575.degree. to 700.degree. C. whereas they will move quickly for even short periods at 900.degree. C. and above. The applicants have discovered a way of using in situ doped amorphous and polycrystalline silicon that not only takes advantage of the reduction in fabrication steps, which is well known, but also of the milder temperature conditions permitted.
Another problem with current wafer fabrication concerns gate dielectric integrity. Silicon dioxide is often used as the thin gate dielectric for transistors or as the interplate dielectric for capacitors. If this thin dielectric layer is exposed outside of a protected processing chamber, it runs the risk of contamination which may eventually cause the layer to break down during use causing a short or other device failure mechanism. Thus, it would be desirable if the process flow allowed "direct transfer" as often as possible, that is, which permitted the wafer to immediately have the next layer formed after the gate oxide layer is formed without any cleaning or other process to avoid this undesirable contamination. Direct transfer results in more reliable gate oxide layers and fewer gate oxide breakdowns.